Redundant components have been used to improve the reliability of a system. For example, Triple Modular Redundancy (TMR) has been used to improve the reliability of a digital processing system, in which a voting circuit compares the redundant results of three redundant circuits that simultaneously perform the same computation to migrate Single Event Upsets (SEU). For example, two-out-of-three voting has been used to elect the final result and eliminate the effect of SEU.
TMR can be used at different levels (e.g., at a module/device level, or at a gate level). For example, an entire module or device may be replicated to generate redundant instances of the module or device; and, the outputs of the redundant instances are compared to each other to vote for the final result. To limit the error propagation, the voting may also be performed at a gate level (e.g., before or after sequential elements) so that the error in one section of a circuit will not propagate into another section of the circuit. For example, FIG. 26 illustrates one TMR approach which triplicates a D-type flip-flop to create redundant instances (e.g., flip-flops 2011, 2013, and 2015) and applies a voter (e.g., voter 2002, which includes AND gates 2021, 2023 and 2025 and OR gate 2027) to process the simultaneous outputs of the redundant instances of the D-type flip-flop to generate a TMR protected output (e.g., 2003). By replacing each of the flip-flops in the design with the redundant instances and the voter (e.g., replacing each flip-flop with an instance of circuit 2000), the design is protected against SEUs occurred in the flip-flops.
For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.